Calvin Deutschbein :: Selected Publications by Year

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• Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance
  S. Aftabjahani, M. Tehranipoor, F. Farahmandi, B. Ahmed, R. Kastner, F. Restuccia, A. Meza, K. Ryan, N. Fern, J. van Woudenberg, R. Velegalati, C. Breunesse, C. Sturton, C. Deutschbein, ,
  2023 IEEE 41st VLSI Test Symposium (VTS) (2022). June 2023.
  doi:10.1109/VTS56346.2023.10140100
  
• Aphrodite: Security Properties of RISC-V
  J. DeYoung, C. Deutschbein
  NWSA-AAASPD 2023 , March 2023.
  [Aphrodite Repository]
  
• Isadora: automated information-flow property generation for hardware security verification
  C. Deutschbein, A. Meza, F. Restuccia, R. Kastner, C. Sturton
  Journal of Cryptographic Engineering (2022). 11 November, 2022.
  doi:10.1007/s13389-022-00306-w
  [Isadora SoC Repository]
• Toward Hardware Security Property Generation at Scale
  C. Deutschbein, A. Meza, F. Restuccia, M. Gregoire, R. Kastner, C. Sturton
  IEEE Security & Privacy (Volume: 20, Issue: 3, May-June 2022) , April 2022.
  doi:10.1109/MSEC.2022.3155376
  [Isadora Repository]
  
• Isadora: Automated Information Flow Property Generation for Hardware Designs
  C. Deutschbein, A. Meza, F. Restuccia, R. Kastner, C. Sturton
  ACM Workshop on Attacks and Solutions in Hardware Security (ASHES), 2021., November 2021.
  doi:10.1145/3474376.3487286
  [Isadora Repository]
  
• Mining Secure Behavior of Hardware Designs
  C. Deutschbein
  University of North Carolina at Chapel Hill
  Doctoral Dissertation, August 2021.
  doi:10.17615/q39e-f161
  
• End-to-End Automated Exploit Generation for Processor Security Validation
  R. Zhang, C. Deutschbein, P. Huang, C. Sturton
  IEEE Design & Test Special Issue: Hardware Security Top Picks, June 2021.
  doi:10.1109/MDAT.2021.3063314
  [Coppelia Repository]
  
• Evaluating Security Specification Mining for a CISC Architecture
  C. Deutschbein, C. Sturton
  Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), December 2020.
  doi:10.1109/HOST45689.2020.9300291
  [Astarte Repository]
  
• Multi-core Cyclic Executives for Safety-Critical Systems
  C. Deutschbein, T. Fleming, A. Burns, S. Baruah
  Science of Computer Programming, March 2019.
  doi:10.1016/j.scico.2018.11.004
• Mining Security Critical Linear Temporal Logic Specifications for Processors
  C. Deutschbein, C. Sturton
  Proceedings of the 2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV), December 2018.
  doi:10.1109/MTV.2018.00013
  [Undine Repository]
  
• End-to-End Automated Exploit Generation for Processor Security Validation
  R. Zhang, C. Deutschbein, P. Huang, C. Sturton
  MICRO-51: Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, October 2018.
  doi:10.1109/MICRO.2018.00071
  [Coppelia Repository]
  
• Multi-core Cyclic Executives for Safety-Critical Systems
  C. Deutschbein, T. Fleming, A. Burns, S. Baruah
  Proceedings of the Third International Symposium on Dependable Software Engineering: Theories, Repositorys, and Applications, SETTA 2017, October 2017.
  doi:10.1016/j.scico.2018.11.004
• Preemptive Uniprocessor EDF Schedulability Analysis with Preemption Costs Considered
  C. Deutschbein, S. Baruah
  Proceedings of the 2016 IEEE Real-Time Systems Symposium (RTSS), November 2016.
  doi:10.1109/RTSS.2016.047
• Performance and energy limits of a processor-integrated FFT accelerator
  T. Thanh-Hoang, A. Shambayati, C. Deutschbein, H. Hoffmann, A. A. Chien
  Proceedings of the 2014 IEEE High Performance Extreme Computing Conference (HPEC), September 2014.
  doi:10.1109/HPEC.2014.7040951